1. Field of the Invention
The invention relates to a synchronous signal generating circuit, and more particularly to a synchronous signal generating circuit of a memory device.
2. Description of the Related Art
A Synchronous Dynamic Random Access Memory (SDRAM) component is a high-density, solid-state, volatile, digital data storage device. Operations of an SDRAM device is that all timing related signals, such as applied control signals, output signals, data bits in both read and write operations, operate in synchronous with the clock signal applied to the device. This feature simplifies the control of memory or system operations and allows the system operating in higher frequencies and provides higher throughput than conventional DRAMs. Synchronizing the memory operation with a clock signal is even more critical for Double Data Rate (DDR) SDRAM components, which provide data and control signal transitions on both the rising and falling edges of the clock signal.
One example signal in a synchronous SDRAM system is a data strobe signal. It is a signal used in write and read operations. Data strobe signal is provided as an input to an SDRAM device when writing data to it. Data strobe signal is synchronized with the clock signal for latching data to be written into the memory device. Conversely, data strobe signal is an output signal generated by the SDRAM when reading data read from it. Data strobe signal is synchronized with the clock signal to latch the data read from the memory.
In a read operation, SDRAM generates data strobe signal synchronously with the clock signal. Ideally, data bits (DQ) and data strobe (DQS) should exhibit little or no skew relative to the applicable clock signal. The degree to which DQ and DQS diverge from synchronicity with the clock signal limits high frequency operations, and is specified by SDRAM manufacturers as DQ output access time (tAC) and DQS output access time (tDQSCK), respectively. One challenge of designing and manufacturing SDRAMs, is to minimize tAC and tDQSCK.
A conventional approach to reduce the skew between the synchronous output signals and the clock signal in an integrated circuit is to use a Delay Locked Loop (DLL). A DLL dynamically adjusts an amount of delay provided by a variable delay line to reduce the phase skew between a synchronous signal which is generated by the DLL and an input clock signal. The current DDR4 Task Group (TG) and Joint Electron Devices Engineering Council (JEDEC) have proposed a new feature called DLL Control Mode. This feature allows enabling or disabling DLL blocks during a self-refresh mode to save power and improve performance. However, there is an issue with one of the key timing parameter tDQSCK to vary unpredictable during the DLL off mode. In the DLL off mode the min/max timing on tDQSCK is unpredictable. Therefore, a novel circuit structure to maintain optimized timing of the tDQSCK is highly required.